This project was done as a course project of the Microprocessors course in a team of four. It involved developing a multi-cycle processor of a given Instruction Set Architecture of 14 instructions, including ADD, NAND, LOAD, STORE, JUMP instructions.
Two implementations of this were done - namely a Multicycle RISC processor and a pipelined version of it. We used Priority Encoders and Hazard Detection Units to reduce latencies, control and data hazards and thus increase the performance.
